CDI64500 – 64-Channel, 18-Bit Current-to-Digital ADC

The CDI64500 is a 64-channel, 18-bit Current-to-Digital ADC ASIC developed by Comport Data. It integrates a charge amplifier and an 18-bit analog-to-digital converter (ADC) in every one of its 64 channels. It is specifically optimized to achieve the lowest possible power consumption and cost per channel, making it ideal for high-channel-count medical imaging systems such as X-ray scanners and CT-scan detectors.

The CDI64500 supports 64 independent channels, each with its own integrated charge amplifier and 18-bit ADC. Multiple CDI64500 devices can be cascaded — up to 16 units can share the same data lines, enabling systems with up to 1,024 simultaneous acquisition channels.

Each of the CDI64500’s 64 channels includes an 18-bit ADC, providing 262,144 discrete digital output codes per channel. This high resolution enables very precise measurement of small charge inputs, which is critical in medical imaging applications where signal fidelity directly impacts image quality.

The CDI64500’s charge amplifier full scale ranges from 1.75 pC to 87.5 pC, depending on the programmed gain setting. The programmable gain capacitor ranges from 0.5 pF to 25 pF, giving designers flexibility to match the charge amplifier to the dynamic range of their detector or sensor array.

The CDI64500 allows gain to be programmed independently for two groups of 32 channels each (Group A: channels 1–32, Group B: channels 33–64). Configuration is performed via an I2C interface, which allows flexible gain settings to be applied digitally without requiring hardware changes.

The CDI64500 consumes less than 1.5 mW per channel. This ultra-low-power design is critical for high-channel-count imaging systems where the cumulative power dissipation across hundreds or thousands of channels would otherwise create significant thermal management challenges.

The CDI64500 uses two interfaces: an LVDS (Low-Voltage Differential Signaling) interface for high-speed data transfer and channel sequencing, and an I2C interface for device configuration (gain programming and other settings). The LVDS interface allows up to 16 CDI64500 devices to share the same data lines when daisy-chained.

The CDI64500 uses Correlated Double Sampling (CDS), a widely adopted technique in precision analog design that significantly reduces low-frequency noise (1/f noise) and offset drift. CDS works by sampling the amplifier output before and after signal acquisition and computing the difference, canceling common-mode noise components.

The CDI64500 is supplied in a custom fpBGA (fine-pitch Ball Grid Array) package. This package type provides a compact footprint with a high pin count, making it suitable for dense multi-chip PCB assemblies typical in medical imaging detector modules.

Yes. The CDI64500 was specifically designed for use in X-ray scanners and CT-scan detector front-ends. Its combination of a 64-channel charge amplifier with 18-bit ADC per channel, ultra-low power consumption (<1.5 mW/channel), high-speed LVDS data interface, and the ability to cascade up to 16 devices makes it an ideal readout IC for large detector arrays in medical imaging.